In order to minimize the electric fields present in a MOSFET where the MOS gate overlaps the drain region, a well-known technique called a lightly doped drain (LDD) has been developed. By using LDD termination techniques, field plate-induced breakdown, which normally limits the BV.sub.dss to approximately 30 volts, is eliminated and the device is then capable of the full avalanche voltage characteristic of the substrate or epitaxial doping concentration. Breakdown voltages of 30-1200 volts have been achieved using LDD techniques. Furthermore, electron-hole pairs that are crated in a LDD transistor are not swept into the gate oxide as hot carriers, and they do not charge the gate oxide and degrade mobility. LDD structures also exhibit a lower gate-to-drain overlap capacitance because the LDD region behaves as a series capacitor. Lower overlap capacitance improves the switching and the high frequency characteristics of the MOSFET.
Lightly doped drain MOSFETs have been implemented in a number of ways. FIG. 1 shows a conventional high voltage LDD using an ion implanted lightly doped drift region, also known as a lateral charge control region or LCC. Notice the structure is asymmetric; the lightly doped region is implanted only o the drain side. The optimum implant dose may vary depending on substrate concentration but is typically around 10.sup.12 dopant atoms cm.sup.-2.
FIG. 2 exhibits a similar structure that uses an epitaxial layer to form the charge control region. The advantage of this technique is that a p+ buried layer can be used for additional field shaping in the vicinity of the gate. Because of the tolerances required in the amount of drift charge dose (typically 1-2.times.10.sup.12 dopant atoms cm.sup.-2), the thin n- epi layer is normally ion implanted to set the amount of charge in the drift similar to the LDD device in FIG. 1. Because of the field shaping available in this structure it is referred to as a "reduced surface field" or RESURF device.
FIG. 3 illustrates how the LDD concept has been applied to low voltage devices used in VLSI. Transistors with gate lengths below 3 .mu.m have electric fields comparable to the aforementioned high voltage devices, even at 5 volt supply voltages; the LDD concept is useful here as well. Because of the small LDD feature size however, it is not possible on such a structure to mask the drift implant so that it will only appear on the drain side. Instead, the drift is formed by the well known "sidewall spacer technique," where the drift is implanted on both sides of the gate. The poly gate is then oxidized at a low temperature to form a sidewall spacer oxide and the n+ source/drain regions are implanted. The resulting device is symmetric.
In all of the devices described thus far, the addition of the lightly doped drain region improves device breakdown but sacrifices low on-state resistance because the drift region acts as a series resistor. Moreover, under some circumstances the drift region can actually limit the current by pinching off via JFET action. This results in poor I.sub.d (sat) characteristics, as shown in FIG. 4, which compared I.sub.d vs. V characteristics for LDD MOS and for conventional MOS. The equivalent model of the high voltage LDD and RESURF structures is shown in FIG. 5A.
In the low voltage LDD transistor the situation is different. The drift region is more heavily doped than the high voltage transistors so that it is unlikely that enough voltage could be applied to the drift for it to pinch off. The drift region then can be modeled simply as a resistor. Because the device is symmetric, this resistor appears on both the source and drain sides of the transistor. The resistance on the source side constitutes source degeneration, a form of negative feedback that reduces the overall device efficiency. The equivalent low voltage circuit model is illustrated in FIG. 5B.
It is possible to increase the drift region concentration somewhat, but not without degrading device breakdown. Specifically, a more heavily doped drift region increases the electric field near the MOS gate and leads to lower breakdown voltages.
An attempt to avoid a compromise between device breakdown and on-state resistance is described in United Kingdom Patent GB 2150746A. One proposed device, shown in FIG. 6, uses a layer of SIPOS (semi-insulating polycrystalline silicon) covering the drift region to create a surface accumulation region that lowers the effective on-state resistance of the transistor. To form the accumulation region, the SIPOS must have a nonzero voltage across it (V.sub.SIPOS &gt;V.sub.source). The SIPOS is slightly conductive so that it forms a resistor with a small leakage current flowing through it and therefore acts as a voltage divider. In so doing, the SIPOS acts as the high voltage termination by spreading out the equipotentials to maintain the breakdown voltage.
The electrical properties of SIPOS are strongly dependent on temperature. Consequently, at low temperatures it is less conductive (becoming more insulator-like) and no longer functions as a voltage termination to improve breakdown or to reduce on-state resistance. At high temperatures it becomes more conductive, resulting in a large leakage through the SIPOS resistor. The application of SIPOS termination techniques has been severely limited due to this strong temperature dependence.
What is needed here is a method to enhance the conductivity of a drift region without requiring a parasitic leakage current. The subject invention uses a biased conductive field plate positioned over the region to induce a surface accumulation region and reduce the drift resistance during "on-state" conduction; the plate is biased to a different potential when the device is in the "off-state", to maintain high voltage blocking capability. Further, because the invention uses a conductive material such as doped polysilicon or metal already available in the process, no special fabrication steps such as SIPOS are required.